Guest Editors' Introduction: Advances in 3-D Integrated Circuits, Systems, and CAD Tools - Part 2

h THREE-DIMENSIONAL INTEGRATION HAS been considered one of the most promising breakthrough technologies achieving higher integration density, better performance, lower power consumption, and smaller form factor. Enabling 3-D integration, however, requires innovation and advancement in manufacturing technology, modeling, design methodologies, and optimization algorithms for physical layout, circuit and system architectures, cooling solutions, testing methodologies, and applications. Thanks to the enormous efforts put into 3-D integration, a few commercial 2.5-D and 3-D products are finally coming into the semiconductor market. These 2.5-D and 3-D products must be just a beginning of the era of 3-D ICs and more general 3-D IC products such as multidie logic-logic-stacked 3-D ICs, manydie-stacked 3-D ICs, and heterogeneous 3-D ICs will be successfully commercialized and appear in the semiconductor market in the future. However, enabling the general 3-D ICs is still very challenging due to various problems such as heat removal, lack of standards and design and analysis tools, and unsatisfactory performance improvement. This special issue highlights recent investigations regarding 3-D integration. The selected papers cover a wide range of topics on 3-D ICs, from manufacturing process and 3-D integration technology to test methodologies, applications, and optimization algorithms. ‘‘Physical Design and CAD Tools for 3-D Integrated Circuits: Challenges and Opportunities,’’ by Kim and Lim, gives an overview of 3-D integration technologies (2.5-D, TSV-based 3-D, inductive-coupling-based 3-D, and monolithic 3-D), then presents challenges and opportunities from various perspectives. It also reviews past works on CAD algorithms for 3-D integration and discusses uncharted problems for each 3-D integration technology. ‘‘Fabrication and Assembly of Cu-RDL-based 2.5-D Low-Cost Through Silicon Interposer (LC–TSI),’’ by Katti et al., presents a low-cost through silicon interposer (LC–TSI) fabrication process. The authors first present an overview of their 2.5-D LC–TSI technology and key challenges to resolve. Then, they provide details on their TSV and Cu-RDL fabrication process, C-o-(C-o-S) assembly, cost reduction, and warpage analysis. Last, they show characterization and measurement results. ‘‘Heat Dissipation Capability of a Package-onPackage Embedded Wafer-Level Package,’’ by Han et al., presents the heat dissipation capability of embedded wafer-level package (eWLP) technology. The authors first show their simulation models and results for thermal analysis of eWLP package and package-on-package (POP) structures. With the models, they analyze thermal effects of passivation materials and find a main heat dissipation path. Then, they propose passive cooling solutions (top cap and package lid) for better heat dissipation. ‘‘A DfT Architecture and Tool Flow for 3-D SICs with Test Data Compression, Embedded Cores, and Multiple Towers,’’ by Papameletis et al., proposes a